1. Field of the Invention
The present invention broadly relates to computer-implemented methods of optimization of manufacturing processes for integrated circuit (IC) layouts, such as methods of lithographic printing of features for forming IC patterns on a semiconductor chip, and particularly to improvements in identifying and prioritizing patterns of an IC design on which to perform optimization of the lithographic process more effectively.
2. Description of the Related Art
In the manufacture of integrated circuits, photolithographic processes are commonly used, in which a wafer is patterned by projecting radiation through a patterned mask to form an image pattern on a photo sensitive material, referred to as a photoresist, or simply resist. The exposed resist material is developed to form openings corresponding to the image pattern, and then the pattern is transferred to the wafer substrate by methods such as etching, as known in the art.
Many methods have been developed to compensate for the image degradation that occurs when the resolution of optical lithography systems approaches the critical dimensions of the lithographic patterns used to form IC's. Critical dimension refers to the feature size and spacing between features and feature repeats (pitch) that are required by the design specifications and are critical for the proper functioning of on-chip devices. When the critical dimensions of an IC pattern approach the resolution of a lithographic system (defined as the smallest dimensions that can be reliably printed by the system), image distortions becomes a significant problem. Today the limited resolution of lithography tools poses a technical challenge in IC manufacture, and this difficulty may increase in the future as critical dimensions become increasingly smaller. In order to make the manufacture of future IC products feasible, lithography tools will be required to achieve adequate image fidelity when the ratio of the minimal critical dimension to resolution of the lithographic system is very low. For instance, extreme ultraviolet (EUV) lithography may not be ready soon enough. Thus, lithography for the 22 nm CMOS chip fabrication process still needs to use a 193 nm light source.
The basic lithography system consists of a light source, a photomask containing the pattern to be transferred to the wafer, a collection of lenses, and a means for aligning existing patterns on the wafer with patterns on the mask. Mask design processes as evoked herein cover many steps from the chip design to the mask fabrication.
Resolution enhancement techniques (RETs) such as OPC (optical proximity correction) are perhaps not sufficient to obtain sufficient printing quality (see Lars W. Liebmann. Layout Impact of Resolution Enhancement Techniques: Impediment or Opportunity?// International Symposium on Physical Design. Monterey, Calif., USA, April 2003).
Amongst other RETs, methods have been proposed for optimizing combinations of source illumination and mask patterns (referred to hereinafter as source-mask optimization or “SMO”) together. Such methods can result in improved process windows (see, for example, U.S. Pat. No. 6,563,566).
SMO has been demonstrated for SRAM type of masks (having high symmetry and periodicity), more particularly for small size of designs. However, SMO methods are computationally expensive. It is therefore impractical to perform a SMO on a full chip layout. Thus, only some selected “hard-to-print” patterns are considered for full optimization. Currently, such patterns are usually identified using a set of predetermined rules that are determined experimentally for a specific chip design. However, the applicability of the rules is limited. Other methods rely on approximate imaging methods but are too slow for many applications.
The limits of SMO methods were addressed by using data compression solutions. Again, the underlying idea is that only those patterns which benefit the most from intensive optimizations should be selected for SMO (see e.g., Kehan Tian et al., Benefits and Trade-Offs of Global Source Optimization in Optical Lithography. // Optical Microlithography XXII. San Jose, Calif., USA. 24 Feb. 2009). According to this solution, a small subset of all patterns extracted from a full chip, also called source binding clips (SBC), is used in the source optimization (SO) to define the source that will then be used for the full mask optimization (MO), reducing significantly the computational requirements. There, the selection of the SBCs is critical, inasmuch as it defines the success of the source for the whole chip.
In a current approach, this subset of clips is selected by clustering the full set and taking one (or more) representatives from each cluster. The basic idea is that clustering aggregates patterns that are very similar, such that a selection of representative patterns is sufficient for the SO. Hence, the SBCs chosen to drive the SO critically depend on the clustering technique.